The present invention relates to increasing accuracy in predicting hot carrier injection (HCI) degradation in semiconductor devices.
In the course of enhancing semiconductor device design and performance, faster circuit operation has been achieved with the reduction of transistor sizes. For designers, attempts to continue to improve device performance face increasing challenges as further reductions in transistor sizes are sought. For example, it is commonly known that a problem with hot carrier injection increases as device sizes shrink.
Hot carrier injection (HCI) occurs as a result of the reduced channel size of sub-micron transistors causing an increase in the electric field, which can allow the carrier to be injected into the gate oxide of the transistor. Over time, the resulting charged gate oxide causes device degradation, raising the threshold voltage and reducing the transconductance. Device testing attempts to determine the rate of degradation due to HCI.
A known method to determine the rate of degradation due to HCI involves the use of an inverter ring oscillator. FIG. 1 illustrates a typical configuration of an inverter ring oscillator circuit 10 that includes an AND gate 11 and an odd number of CMOS inverters 12 connected in cascade to form a loop. The series of inverters 12 causes the output signal of the inverter ring oscillator 10 to oscillate/xe2x80x98ringxe2x80x99 between an applied voltage potential and a ground potential. In operation, the inverter ring oscillator 10 is subjected to high voltage stress to evaluate frequency degradation and determine the voltage acceleration effect on HCI in CMOS integrated circuits. Specifically, the CMOS circuits are only subjected to the HCI damage sufficiently during the transitions, and the number of transitions depends on the stress voltages, with an increase in voltage increasing the number of transitions. While the degradation due to frequency is reflected by running the ring oscillators circuits at various voltages, the application of the differing voltages reduces the ability to detect degradation due to the voltage itself. Thus, because the typical ring oscillators run through different numbers of transitions under different stress voltages, the frequency degradation lifetime calculation is confounded with voltage acceleration and the different number of transitions.
To obtain a more accurate voltage acceleration factor due to HCI, a need exists for a test structure that can isolate the voltage acceleration factor directly during HCI degradation testing. The present invention addresses such a need.
Aspects for increasing accuracy in predicting HCI degradation in semiconductor devices are described. The aspects include a gated ring oscillator structure utilized to perform HCI degradation testing with controlling of the gated ring oscillator structure to isolate voltage acceleration degradation from frequency degradation directly during the HCI degradation testing. Further included is a plurality of ring oscillators coupled in series, and first and second control logic for the plurality of ring oscillators for enabling selection of gated operation of the plurality of ring oscillators, wherein each ring oscillator performs a same number of transitions to allow an accurate assessment of HCI degradation based solely on voltage acceleration.
With the present invention, the accuracy in predicting HCI degradation, such as in microprocessors, using ring oscillator test structures is increased by increasing the accuracy of the extracted voltage acceleration coefficient from ring oscillators. The test structure, which includes gated ring oscillators in the present invention, allows control over the logic transitions, so that by going through the same number of logic transitions, the AC HCI stress experiment undergoes true voltage acceleration. These and other advantages of the present invention will become readily apparent from the following detailed description and accompanying drawings.